SPI0 Ext_RAM timing compensation register.
| SPI_SMEM_TIMING_CLK_ENA | Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL. |
| SPI_SMEM_TIMING_CALI | Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. |
| SPI_SMEM_EXTRA_DUMMY_CYCLELEN | Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set. |